5152d0c9f7
Foundation for replacing fold's dead/abstract binary encoder with a real
SSA P-Code frontend. Verified root-cause gap: serializeBinaryIR() emits only
data-discovery nodes (sections/strings/imports/exports); the control-flow
BinaryExprKind values (BasicBlock/CallSite/...) are never constructed, so the
Z3-BB encoder's encodable filter is always empty and encodeBinaryBBs never
runs — hence 0 binary Z3 findings. The P-Code pipeline supersedes that path.
Phase 0 — docs/internal/ghidra-pcode-integration-research.md: P-Code opcode
core, the decompiler C++ embedding API (LoadImage/SleighArchitecture/Funcdata),
the CORE+DECCORE+SLEIGH source sets, no-bison finding, and pypcode as build
reference.
Phase 1 — vendored Ghidra decompiler at pinned commit (Ghidra_12.1_build,
7e89d94e34...) under third_party/ghidra-decompiler/ (cpp + AArch64 specs +
Apache-2.0 LICENSE + VENDOR.md + .gitignore for build artifacts). Validated by
hand on this clang-21/macOS toolchain:
- full SSA engine (CORE+DECCORE+SLEIGH, 80 files incl. heritage/funcdata/
action) compiles clean, -std=c++11 -O2, NO BFD, NO bison (generated
parsers are committed upstream; ruleparse isn't in the lib set);
- sleigh compiler builds; AArch64 .slaspec -> .sla compiles;
- tools/pcode_dump.cpp (custom LoadImage, no BFD) lifts the real arm64
sym._div_by_zero_direct to correct P-Code: `mov w9,#0 -> COPY(const 0)`,
`sdiv -> INT_SDIV(w8,w9)` — divisor zero-ness explicit in the data flow,
so the Phase-3 encoder proves div-by-zero trivially, multi-arch.
Not yet meson-wired (next step) and no fold-side IR/encoder yet (Phase 2-3);
this commit is the validated vendor + smoke tool.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
79 lines
3.7 KiB
XML
79 lines
3.7 KiB
XML
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<language_definitions>
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slafile="AARCH64.sla"
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processorspec="AARCH64.pspec"
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manualindexfile="../manuals/AARCH64.idx"
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id="AARCH64:LE:64:v8A">
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<description>Generic ARM64 v8.5-A LE instructions, LE data, missing some 8.5 vector</description>
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<compiler name="golang" spec="AARCH64_golang.cspec" id="golang"/>
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<compiler name="Swift" spec="AARCH64_swift.cspec" id="swift"/>
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<external_name tool="gnu" name="aarch64"/>
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<external_name tool="Golang.register.info.file" name="AARCH64_golang.register.info"/>
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<external_name tool="qemu" name="qemu-aarch64"/>
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</language>
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<language processor="AARCH64"
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endian="big"
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instructionEndian="little"
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size="64"
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variant="v8A"
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version="1.6"
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slafile="AARCH64BE.sla"
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processorspec="AARCH64.pspec"
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manualindexfile="../manuals/AARCH64.idx"
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id="AARCH64:BE:64:v8A">
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<description>Generic ARM64 v8.5-A LE instructions, BE data, missing some 8.5 vector</description>
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<compiler name="default" spec="AARCH64.cspec" id="default"/>
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<compiler name="golang" spec="AARCH64_golang.cspec" id="golang"/>
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<external_name tool="gnu" name="aarch64"/>
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slafile="AARCH64.sla"
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manualindexfile="../manuals/AARCH64.idx"
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manualindexfile="../manuals/AARCH64.idx"
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