5152d0c9f7
Foundation for replacing fold's dead/abstract binary encoder with a real
SSA P-Code frontend. Verified root-cause gap: serializeBinaryIR() emits only
data-discovery nodes (sections/strings/imports/exports); the control-flow
BinaryExprKind values (BasicBlock/CallSite/...) are never constructed, so the
Z3-BB encoder's encodable filter is always empty and encodeBinaryBBs never
runs — hence 0 binary Z3 findings. The P-Code pipeline supersedes that path.
Phase 0 — docs/internal/ghidra-pcode-integration-research.md: P-Code opcode
core, the decompiler C++ embedding API (LoadImage/SleighArchitecture/Funcdata),
the CORE+DECCORE+SLEIGH source sets, no-bison finding, and pypcode as build
reference.
Phase 1 — vendored Ghidra decompiler at pinned commit (Ghidra_12.1_build,
7e89d94e34...) under third_party/ghidra-decompiler/ (cpp + AArch64 specs +
Apache-2.0 LICENSE + VENDOR.md + .gitignore for build artifacts). Validated by
hand on this clang-21/macOS toolchain:
- full SSA engine (CORE+DECCORE+SLEIGH, 80 files incl. heritage/funcdata/
action) compiles clean, -std=c++11 -O2, NO BFD, NO bison (generated
parsers are committed upstream; ruleparse isn't in the lib set);
- sleigh compiler builds; AArch64 .slaspec -> .sla compiles;
- tools/pcode_dump.cpp (custom LoadImage, no BFD) lifts the real arm64
sym._div_by_zero_direct to correct P-Code: `mov w9,#0 -> COPY(const 0)`,
`sdiv -> INT_SDIV(w8,w9)` — divisor zero-ness explicit in the data flow,
so the Phase-3 encoder proves div-by-zero trivially, multi-arch.
Not yet meson-wired (next step) and no fold-side IR/encoder yet (Phase 2-3);
this commit is the validated vendor + smoke tool.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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4.3 KiB
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#
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# Apple AARCH64 extended matrix instructions
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# Contents based on evolving information published on Web
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#
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#
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define pcodeop __amx_ldx;
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define pcodeop __amx_ldy;
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define pcodeop __amx_stx;
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define pcodeop __amx_sty;
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define pcodeop __amx_ldz;
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define pcodeop __amx_stz;
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define pcodeop __amx_ldzi;
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define pcodeop __amx_stzi;
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define pcodeop __amx_extrx;
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define pcodeop __amx_extry;
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define pcodeop __amx_fma64;
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define pcodeop __amx_fms64;
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define pcodeop __amx_fma32;
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define pcodeop __amx_fms32;
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define pcodeop __amx_mac16;
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define pcodeop __amx_fma16;
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define pcodeop __amx_fms16;
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define pcodeop __amx_enable;
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define pcodeop __amx_disable;
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define pcodeop __amx_vecint;
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define pcodeop __amx_vecfp;
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define pcodeop __amx_matint;
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define pcodeop __amx_matfp;
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define pcodeop __amx_genlut;
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with : ImmS_ImmR_TestSet=1 {
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AMXAddr: is Rd_GPR64 {
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addr:8 = Rd_GPR64 & 0x00FFFFFFFFFFFFFF;
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export addr;
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}
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AMXRegOff: is Rd_GPR64 {
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registerOff:8 = (Rd_GPR64 >> 56) & 0x1F;
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export registerOff;
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}
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AMXSize: is Rd_GPR64 {
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local size = ((Rd_GPR64 >> 62) & 1);
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size = zext(size == 0) * 0x40 | zext(size ==1 ) * 0x80;
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export size;
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}
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:__amx_ldx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=0 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_ldx(Rd_GPR64);
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}
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:__amx_ldy Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=1 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_ldy(Rd_GPR64);
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}
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:__amx_stx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=2 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_stx(Rd_GPR64);
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}
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:__amx_sty Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=3 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_sty(Rd_GPR64);
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}
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:__amx_ldz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=4 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_ldz(Rd_GPR64);
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}
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:__amx_stz Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=5 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_stz(Rd_GPR64);
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}
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:__amx_ldzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=6 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_ldzi(Rd_GPR64);
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}
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:__amx_stzi Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=7 & AMXAddr & AMXRegOff & AMXSize & Rd_GPR64
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{
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__amx_stzi(Rd_GPR64);
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}
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:__amx_extrx Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=8 & Rd_GPR64
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{
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__amx_extrx(Rd_GPR64);
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}
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:__amx_extry Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=9 & Rd_GPR64
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{
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__amx_extry(Rd_GPR64);
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}
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:__amx_fma64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=10 & Rd_GPR64
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{
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__amx_fma64(Rd_GPR64);
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}
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:__amx_fms64 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=11 & Rd_GPR64
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{
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__amx_fms64(Rd_GPR64);
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}
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:__amx_fma32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=12 & Rd_GPR64
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{
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__amx_fma32(Rd_GPR64);
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}
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:__amx_fms32 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=13 & Rd_GPR64
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{
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__amx_fms32(Rd_GPR64);
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}
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:__amx_mac16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=14 & Rd_GPR64
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{
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__amx_mac16(Rd_GPR64);
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}
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:__amx_fma16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=15 & Rd_GPR64
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{
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__amx_fma16(Rd_GPR64);
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}
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:__amx_fms16 Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=16 & Rd_GPR64
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{
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__amx_fms16(Rd_GPR64);
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}
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:__amxdisable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=1
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{
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__amx_disable();
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}
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:__amxenable is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=17 & b_0004=0
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{
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__amx_enable();
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}
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:__amx_vecint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=18 & Rd_GPR64
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{
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__amx_vecint(Rd_GPR64);
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}
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:__amx_vecfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=19 & Rd_GPR64
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{
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__amx_vecfp(Rd_GPR64);
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}
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:__amx_matint Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=20 & Rd_GPR64
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{
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__amx_matint(Rd_GPR64);
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}
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:__amx_matfp Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=21 & Rd_GPR64
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{
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__amx_matfp(Rd_GPR64);
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}
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:__amx_genlut Rd_GPR64 is b_2431=0x00 & b_1623=0x20 & b_1215=1 & b_1011=0 & b_0509=22 & Rd_GPR64
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{
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__amx_genlut(Rd_GPR64);
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}
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} |