5152d0c9f7
Foundation for replacing fold's dead/abstract binary encoder with a real
SSA P-Code frontend. Verified root-cause gap: serializeBinaryIR() emits only
data-discovery nodes (sections/strings/imports/exports); the control-flow
BinaryExprKind values (BasicBlock/CallSite/...) are never constructed, so the
Z3-BB encoder's encodable filter is always empty and encodeBinaryBBs never
runs — hence 0 binary Z3 findings. The P-Code pipeline supersedes that path.
Phase 0 — docs/internal/ghidra-pcode-integration-research.md: P-Code opcode
core, the decompiler C++ embedding API (LoadImage/SleighArchitecture/Funcdata),
the CORE+DECCORE+SLEIGH source sets, no-bison finding, and pypcode as build
reference.
Phase 1 — vendored Ghidra decompiler at pinned commit (Ghidra_12.1_build,
7e89d94e34...) under third_party/ghidra-decompiler/ (cpp + AArch64 specs +
Apache-2.0 LICENSE + VENDOR.md + .gitignore for build artifacts). Validated by
hand on this clang-21/macOS toolchain:
- full SSA engine (CORE+DECCORE+SLEIGH, 80 files incl. heritage/funcdata/
action) compiles clean, -std=c++11 -O2, NO BFD, NO bison (generated
parsers are committed upstream; ruleparse isn't in the lib set);
- sleigh compiler builds; AArch64 .slaspec -> .sla compiles;
- tools/pcode_dump.cpp (custom LoadImage, no BFD) lifts the real arm64
sym._div_by_zero_direct to correct P-Code: `mov w9,#0 -> COPY(const 0)`,
`sdiv -> INT_SDIV(w8,w9)` — divisor zero-ness explicit in the data flow,
so the Phase-3 encoder proves div-by-zero trivially, multi-arch.
Not yet meson-wired (next step) and no fold-side IR/encoder yet (Phase 2-3);
this commit is the validated vendor + smoke tool.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
102 lines
5.4 KiB
XML
102 lines
5.4 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<processor_spec>
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<properties>
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<property key="addressesDoNotAppearDirectlyInCode" value="true"/>
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<property key="allowOffcutReferencesToFunctionStarts" value="false"/>
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<property key="useNewFunctionStackAnalysis" value="true"/>
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<property key="emulateInstructionStateModifierClass"
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value="ghidra.program.emulation.AARCH64EmulateInstructionStateModifier"/>
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<property key="useropLibs" value="aarch64"/>
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<property key="assemblyRating:AARCH64:BE:64:v8A" value="PLATINUM"/>
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<property key="assemblyRating:AARCH64:LE:64:v8A" value="PLATINUM"/>
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</properties>
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<programcounter register="pc"/>
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<!-- The context_data's context_set initializes the given registers to the given values. -->
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<context_data>
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<context_set space="ram">
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<!-- These context registers are only modified by the user, e.g. with the "Set Registers..." command. -->
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<set name="ShowPAC" val="0" description="1 to show PAC operations in decompiler"/>
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<set name="PAC_clobber" val="0" description="1 to let PAC operations overwrite their operands in decompiler"/>
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<set name="ShowBTI" val="0" description="1 to show BTI effects in decompiler"/>
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<set name="ShowMemTag" val="0" description="1 to show memory tag checks in decompiler"/>
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</context_set>
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</context_data>
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<default_symbols>
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<symbol name="Reset" address="ram:0x0" entry="true"/>
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</default_symbols>
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<volatile outputop="cWrite" inputop="cRead">
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<range space="register" first="0x1000" last="0x2fff"/>
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</volatile>
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<register_data>
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<register name="z0" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z1" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z2" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z3" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z4" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z5" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z6" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z7" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z8" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z9" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z10" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z11" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z12" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z13" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z14" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z15" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z16" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z17" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z18" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z19" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z20" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z21" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z22" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z23" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z24" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z25" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z26" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z27" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z28" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z29" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z30" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="z31" group="SVE" vector_lane_sizes="1,2,4,8"/>
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<register name="q0" vector_lane_sizes="1,2,4,8"/>
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<register name="q1" vector_lane_sizes="1,2,4,8"/>
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<register name="q2" vector_lane_sizes="1,2,4,8"/>
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<register name="q3" vector_lane_sizes="1,2,4,8"/>
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<register name="q4" vector_lane_sizes="1,2,4,8"/>
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<register name="q5" vector_lane_sizes="1,2,4,8"/>
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<register name="q6" vector_lane_sizes="1,2,4,8"/>
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<register name="q7" vector_lane_sizes="1,2,4,8"/>
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<register name="q8" vector_lane_sizes="1,2,4,8"/>
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<register name="q9" vector_lane_sizes="1,2,4,8"/>
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<register name="q10" vector_lane_sizes="1,2,4,8"/>
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<register name="q11" vector_lane_sizes="1,2,4,8"/>
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<register name="q12" vector_lane_sizes="1,2,4,8"/>
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<register name="q13" vector_lane_sizes="1,2,4,8"/>
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<register name="q14" vector_lane_sizes="1,2,4,8"/>
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<register name="q15" vector_lane_sizes="1,2,4,8"/>
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<register name="q16" vector_lane_sizes="1,2,4,8"/>
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<register name="q17" vector_lane_sizes="1,2,4,8"/>
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<register name="q18" vector_lane_sizes="1,2,4,8"/>
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<register name="q19" vector_lane_sizes="1,2,4,8"/>
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<register name="q20" vector_lane_sizes="1,2,4,8"/>
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<register name="q21" vector_lane_sizes="1,2,4,8"/>
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<register name="q22" vector_lane_sizes="1,2,4,8"/>
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<register name="q23" vector_lane_sizes="1,2,4,8"/>
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<register name="q24" vector_lane_sizes="1,2,4,8"/>
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<register name="q25" vector_lane_sizes="1,2,4,8"/>
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<register name="q26" vector_lane_sizes="1,2,4,8"/>
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<register name="q27" vector_lane_sizes="1,2,4,8"/>
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<register name="q28" vector_lane_sizes="1,2,4,8"/>
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<register name="q29" vector_lane_sizes="1,2,4,8"/>
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<register name="q30" vector_lane_sizes="1,2,4,8"/>
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<register name="q31" vector_lane_sizes="1,2,4,8"/>
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</register_data>
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</processor_spec>
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